Insulated gate field effect transistors are currentcontrolling, microelectronic devices constructed primarily of semiconductive thin films to which dopant impurities are added at designated device regions. These doped regions include a source region, a drain region, and a channel region. An electrical potential applied across the source and drain regions generates a current which flows through the channel when the device is in the "on" state. The current between the source and drain is modulated by controlling the channel resistance.
Generally, IGFETs can be divided into enhancement mode and depletion mode devices. In both enhancement and depletion mode IGFETs, channel resistance is controlled by an externally applied electric field provided by an insulated gate electrode. The gate electrode is positioned such that it produces an electric field perpendicular to the flow of current through the device channel. In an enhancement mode IGFET, a layer of semiconductive material disposed between the source and drain is doped with impurities to form a region of high resistance. The device is "normally-off" or current blocking at zero gate voltage. In this state, the resistance of the semiconductor material interadjacent the source and drain is sufficiently large such that no drain current flows. When a potential of appropriate polarity is applied to the gate electrode, free majority charge carriers are drawn toward the gate to form an inversion layer in the device channel at the interface of the channel and the gate insulator. In the inversion layer, the charge carriers are the same type as in the source and drain, so they create a highly conductive channel electrically linking the source and drain. This is the on-state in an enhancement mode device, in which the field induced channel allows a drain current to flow.
In the channel region of a depletion mode IGFET, the semiconductor material disposed between source and drain is doped with impurities to produce a lower resistance, "normally-on" channel through which working current can flow with no voltage applied to the gate. By biasing the gate electrode appropriately, a gate field is produced which extends through the gate insulator and into the channel. The gate field repels majority charge carriers, creating a space charge depletion region in the channel. Increasing the gate voltage increases the region of charge carrier depletion which in turn raises the channel resistance. When the depletion region extends completely across the channel, the current between the source and drain is blocked by the channel resistance. This is the "off-state". The gate voltage required to turn off a depletion mode IGFET is commonly referred to as the "pinchoff" voltage.
IGFETs have received renewed interest recently for use as power transistors. By decreasing channel resistance, depletion mode IGFETs can be manufactured which conduct relatively high currents.
One such high-power depletion mode IGFET, referred to as a "J-MOS" transistor, is disclosed in U.S. patent application Ser. No. 552,409 filed Nov. 16, 1983, now U.S. Pat. No. 4,611,220, filed in the name of B. A. MacIver. The J-MOS is constructed on an insulating substrate such as sapphire or silicon dioxide. In a vertically arranged embodiment, the insulator is buried in a semiconductive film, portions of which comprise the source, channel and drain. Utilizing the J-MOS design, IGFETs with highly conductive channels can be turned off. This is made possible by the addition of a novel, island-like pn junction located at the channel gate insulator interface. A voltage applied to the gate to deplete the channel of majority charge carriers simultaneously places the island-like pn junction in reverse bias. Prior to the J-MOS design, the large gate voltages needed to pinch off current through highly conductive channels caused unwanted thermal generation of minority carriers which accumulated beneath the gate insulator. These minority carriers created an inversion layer or electrostatic shield between the gate and the channel which precluded complete channel depletion. The reverse biased J-MOS pn channel junction eliminates this inversion layer by acting as a sink for thermally generated minority carriers. The J-MOS design therefore allows high-power IGFETs to be controlled over their full dynamic range.
However, the J-MOS transistor design described above requires a bulk semiconductive film disposed on an insulator or, alternatively, incorporates an insulator within the film. As those skilled in the art will appreciate, semiconductor-on-insulator devices are costly to manufacture due to fabrication complexity and the utilization of expensive insulators such as sapphire. Therefore, it would be desirable to design a J-MOS transistor-type device which does not require an insulative substrate or buried insulator. We have devised such a device.